Give the following datapath in each part, what will be the signal value in $($i$),($ii$),($iii$),$ and

$($iv$),$ Please specify the answers according to the BUS width. No CREDIT will be given if

the answer is different BUS width.

a$.,$ add $$v1,$$$t1,$$$t8,$ assume $$t1=0x00001124$ and $$t8=0xFFFF$ FFF$0$

b$.$ beq $$s0,$$$s1,0xFFF0,$ assume $PC=040001200,$$$s0=0x000010AA,$$$s1=$

$0$x$000010$AA$.$ c$.$ lw $$t0,48($$$s0),$ assume $$t0=056781234,$$$s0=080000048$

$2.$ The following MIPS assembly code is being executed on a single$-$cycle process as shown in the figure below. a$.$ During the sixth time cycle of processing, which register will be read and which

register will be written?

b$.$ During the sixth time cycle of processing what is the value of the second input of the

ALU stage?

c$.$ At the end of the sixth time cycle of processing, what are the values of registers, St$7,$

$$t8,$ and $$t9?$

Assume a newly designed microprocessor has $8$ pipeline stages, and it is perfectly

pipelined. Answer the following questions:

a$.$ How much speedup the new processor will achieve compared to the non$-$

pipelined processor?

b$.$ The new processor has $8$ pipeline stages, and each stages takes $6\mathrm{.}0ns$ to complete.

When the following MIPS assembly program in executed, how much faster is the

new pipelined processor against a non$-$pipelined processor? $[$Assume the non$-$

pipelined processor requires $40ns$ to complete $1$ instruction.$]$ Assume the below instructions are being executed in a single$-$cycle processor, what

would be the following control signals $($RegDst$,$ ALUSre, MemtoReg, Branch, Jump,

ALU Control$)?$

a$.$ sub $$t5,$$$t3,$$$t2$

b$.$ beq $$v1,$$$t1,$ Target

c$.1w$$$t0,200($$$s0)$

Consider the following MIPS assembly program running in a $5$ stage pipeline processor

and answer the following questions:

a$.$ List all the data hazards, specify the type.

b$.$ Assume that only "nop" instruction can be added to resolve the data hazards found in part

a$.$ How many "nop" instructions are needed?

c$.$ Draw pipeline diagram with the hardware methods introduce in this course to resolve the

data hazard found in part $($a$).$