Given a 32 bit byte addressable machine. Let us suppose we have the following byte address accesses 0, 1, 2, 3, 8, 9, 10, 11, 4, 5, 6, 7, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8. a) Given a 2-way set associative cache in which block size is 1 word and can store a LRU (least recently used) based cache replacement policy. For each access indicate whether it is a hit or miss and the state of the cache. For the state of the cache you can just notate the word address at each location b) Redo the same calculation for a 4 way set associative cache with the same total capacity and block size