Given a dividend a and a divisor b, the restoring division algorithm calculates the quotient q and the remainder r such that a = b x q + r and r

Figure 1 shows the schematic diagram of a restoring divider. There are three registers: reg_b, reg_r, and reg_q, for storing the divisor b, a remainder r, and quotient q respectively. Initially, reg_q stores the dividend a. A subtracter is used to subtract b from the partial remainder. The MSB of the output of the subtracter is used to determine whether the result of the subtraction is negative or not. The multiplexer over reg_q is used to load a initially and to shift the content of reg_q (a and q) to the left later. The multiplexer over reg_r implements the restoring. If the result of the subtraction is negative, the multiplexer selects the original partial remainder. Otherwise, it selects the result of the subtraction. At each iteration, one bit of q is obtained from the sign bit of the subtracter result and written to the LSB of the reg_q.

Write a behavioral Verilog code describing Figure 1.

b[15:00] clk re sub mux al31:00] [30:00] mux re r[15:00] 131:00] b[15:00] clk re sub mux al31:00] [30:00] mux re r[15:00] 131:00]