Given an $8086$ based system with following specifications,

CPU clock is $10MHz$ in minimum mode operation.

Using $8KB$ SRAM devices to implement $32KB$ SRAM at starting address $00000H.$

Using $16KB$ EPROM devices to implement $64KB$ EPROM ends at the upper address FFFFFH$.$

Answer the following questions:$-$

a$)$ The used crystal oscillator frequency is

$20MHz$

$10MHz$

$30MHz$

$40MHz$

b$)$ The peripheral clock frequency is

$20MHz$

$3\mathrm{.}333MHz$

$2\mathrm{.}5MHz$

$5MHz$

c$)$ The number of required SRAM devices is

d$)$ The number of required EPROM devices is

e$)$ The ending address of the implemented $32KB$ SRAM subsystem is

H$.$

f$)$ The starting address of the implemented $64KB$ EPROM subsystem is

g$)$ The number of address lines involved in the generation the Chip Select signal for SRAM device is

h$)$ The number of address lines involved in the generation the Chip Select signal for EPROM device is

i$)$ Address lines that distinguish the generation of Chip Selects for different SRAM devices are

$A_{13}{A}_{14}$

$A_{12}{A}_{13}$

$A_{14}{A}_{15}$

$A_{13}{A}_{14}{A}_{15}$

j$)$ Address lines that distinguish the generation of Chip Selects for different EPROM devices are

$A_{13}{A}_{14}$

$A_{14}{A}_{15}{A}_{16}$

$A_{15}{A}_{16}$

$A_{14}{A}_{15}$