Given the 'basic' pipeline shown below, with the stages: Instruction Fetch, Instruction Decode, Execute Address, Memory Access, Write Back:

THIS IS THE FOLLOWING CODE:

add x3, x1, x2 // x3 = x1 + x2 st x3, 2(x4) // mem[2+x4] = x1 beq x3,x5,L // if x3==x5 branch to L

THIS IS A MANUAL TEST EXAMPLE:

Q1. FILL IN THE FOLLOWING BLANKS FOUND IN SQUARE BRACKETS (Note: some questions maybe multiple choice denoted as / for each option) :

Instruction Fetch: read the instruction [ENTER INSTRUCTION NUMBER] at address [FILL IN ADDRESS NUMBER] and increment the PC to the value [ENTER VALUE]

Instruction Decode: decode the [FILL ANSWER] instruction, read the source registers [FILL REGISTER NUMBER] and [FILL REGISTER NUMBER]from the register file

Execute Address : perform the ALU operation [ADD/ SUB/ MUL/ DIV/ REM/ AND/ OR/ XOR] on the value read from the registers[FILL REGISTER NUMBER] and the immediate value [FILL REGISTER NUMBER]

Memory Access: write the value read from register [FILL ANSWER] to the address calculated by the ALU

Write Back: [there is no writeback / write the ALU result back to register x1 / write the ALU result to the register x4]

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|} \hline Address & Instruction & Clock 1 & Clock 2 & Clock 3 & Clock 4 & Clock 5 & Clock 6 & Clock 7 & Clock 8 \\ \hline 0000 & add x3,1,2 & IF & ID & EX & & WB & & & \\ \hline 0004 & st x1,2(4) & & IF & ID & EX & MEM & WB & & \\ \hline 0008 & beq x3,5,L & & & IF & ID & EX & MEM & WB & \\ \hline \end{tabular}