Given the following counter circuit, with asynchronous load and asynchronous clear: Voc QAD GAI 21 CLK Binary Counter to Insert numeric values between 0 to 15 This counter counts from Q2 - Fill the state table of the given circuit: A(t) BDX A(t+1) B(t+1) 0 ol Z 0 0 0 0 1 1 0 1 0 1 0 1 1 1 0 0 1 B 1 O 1 0 1 1 0 0 1 1 1 1 What is one disadvantage of an S-R latch? Select one: a. Invalid State O b. It has one output C. It has no Enable input d. It has no clock input To make the following register in shift left mode, DC should be equal to DA DB DC Select one: a. External data (Serial Input) b. B . CA dows Loc. Assume you have the following state table: A(t) B(t) A(t+1) B(t+1) 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 0 If you are using D-flip-flops then the simplify DA, and DB are Select one: a. DA=AB+AB DB=AB UAB b. DA=A, DB=B C. DA=1. DB=0 d. DA=0. DB=1 Analyze the following sequential Cucut: OUX 01 Winte the input and output squetons (most simplified form) DA Given the following counter circuit, with asynchronous load and asynchronous clear: Voc QAD GAI 21 CLK Binary Counter to Insert numeric values between 0 to 15 This counter counts from Q2 - Fill the state table of the given circuit: A(t) BDX A(t+1) B(t+1) 0 ol Z 0 0 0 0 1 1 0 1 0 1 0 1 1 1 0 0 1 B 1 O 1 0 1 1 0 0 1 1 1 1 What is one disadvantage of an S-R latch? Select one: a. Invalid State O b. It has one output C. It has no Enable input d. It has no clock input To make the following register in shift left mode, DC should be equal to DA DB DC Select one: a. External data (Serial Input) b. B . CA dows Loc. Assume you have the following state table: A(t) B(t) A(t+1) B(t+1) 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 0 If you are using D-flip-flops then the simplify DA, and DB are Select one: a. DA=AB+AB DB=AB UAB b. DA=A, DB=B C. DA=1. DB=0 d. DA=0. DB=1 Analyze the following sequential Cucut: OUX 01 Winte the input and output squetons (most simplified form) DA