Given the following specification for a simple synchronous bus protocol, design and implement a Verilog module that represents a master device. The bus protocol has the following signals: $$ Address Bus: A $8-$bit bus to specify the slave device address. $$ Data Bus: A $32-$bit bus for data transfer. $$ Read$/$Write Enable: A single$-$bit signal to indicate whether a read or write operation is in progress. $$ Valid: A single$-$bit signal to indicate that a valid address and data are on the bus. $$ Ready: A single$-$bit signal from the slave device indicating that it is ready to respond. $$ Clock: A system clock signal. The master device should: $$ Generate a valid address and data on the bus. $$ Assert the Valid signal. $$ Wait for the Ready signal from the slave device. $$ If the Ready signal is asserted, deassert the Valid signal and wait for the slave device to place the data on the bus $($for read operations$).$