Given the following t

As always, use good coding practices as outlined in class and in your textbook. For each problem include your code, an image of the RTL view of your circuits, as well as your simulation outputs showing that your circuit works.

Problem $1.$

Given the following types and signals:

type arr $1$ is array $(8$ downto $0)$ of std$\_$logic:

type arr$\_2$ is array $(1$ to $4)$ of arr $1$;

signal a: boolean vector $(1$ to $5)$ ;

signal b: std$\_$logic$\_$vector $(10$ downto $0)$;

signal c: arr $1$ i

signal d; arr$-2$;

signal $x$ : std logict

signal y: std$\_$logic$\_$vector $(31$ downto $0)$:

signal z: arr$-1,$

signal wi arr$-2$i

Iemplement a circuit that does the following:

sets $x$ to $\text{'}1\text{'}$ if $y$ contains only zeros

Sets all the bits of $w$ to zerosypes and signals:

type arr$\_1$ is array $(8$ downto $0)$ of std$\_$logic;

type arr$\_2$ is array $(1$ to $4)$ of arr$\_1$;

signal a: boolean$\_$vector $(1$ to $5)$;

signal b: std$\_$logic$\_$vector $(10$ downto $0)$;

signal c: arr$\_1$;

signal d: arr$\_2$;

signal x: std$\_$logic;

signal y: std$\_$logic$\_$vector $(31$ downto $0)$;

signal z: arr$\_1$;

signal w: arr$\_2$;

Implement a circuit that does the following:

$1)$ sets x to $\text{'}1\text{'}$ if y contains only zeros

$2)$ Sets all the bits of w to zeros

Apologies but can you please help with the code here. I$\text{'}$m confused by how to code all this in VHDL spectiifically.