Given these pipeline stage latencies, repeat the speedup calculation from c$),$ taking into account the $($possible$)$ change in clock cycle time. Assume that the latency ID stage increases by $50\%$ and the latency of the EX stage decreases by $10$ps when branch outcome resolution is moved from EX to ID$.$

f$)$ Assuming stall$-$on$-$branch and no delay slots, what is the new clock cycle time and execution time of this instruction sequence if beq address computation is moved to the MEM stage? What is the speedup from this change? Assume that the latency of the EX stage is reduced by $20$ ps and the latency of the MEM stage is unchanged when branch outcome resolution is moved from EX to MEM.