Given two processors $P$ and $Q$ running at $2\mathrm{.}8$ GHz and $3\mathrm{.}0$ GHz respectively. These two machines were designed based on the same ISA. The instructions are classified into $4$ types: integer, memory, branch and floating$-$point. Due to the constraint of different frequency objectives, these $2$ processors have different instruction latencies as shown in the table. Also note, both processors are singleissue$,$ non$-$pipelined. You are asked to evaluate the performance by running a benchmark program K $.$ The instructions breakdown for K is shown in the table.

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$\backslash$table$[[\backslash$table$[[$Instruction$],[$Types$]],\backslash$table$[[$Instruction$],[$Latency for $P$