Having trouble very important assignment quick response would be appreciated. Please draw on piece of paper or something online that lets you draw. Thank You!!

Suppose the following pipeline is designed for the integer and the floating point

parts of the DLX processor. EX is integer ALU operation. A$1,$ A$2$ represent floating

point Add$/$Subtract and are internally pipelined. M$1,$ M$2,$ M$3$ represent floating point

multiply and also is internally pipelined.

For the following parts, show the number of clock cycles needed to execute the

code, forwarding and feedback requirements, and stall detection logic.

ADDF F$6,$ F$3,$ F$2$

SUBF F$2,$ F$8,$ F$7$

DIVF F$8,$ F$2,$ F$8$