Hello, I have this task to code using VHDL and Im stuck. The clock is positive edged triigered and there is a switch to that are programmed as inputs. Im suppose to program this binary counter such that if we register the rising edge of the clock then we start the counting. Then if the switch is =0 then we count upwards and if the switch is =1 then we count downwards. Im on the process part. Can someone help me with how Im going to program this?

cessing Tools Window Help Home 03 Vhdl1.vhd 1 Tibrary jeee 2 use ieee.std_ logic 1164.all; 3 use ieee.numeric std.all; 5 entity AOI is port ( clock 50: in std logic; 9 edr: out std logic_ vector (4 downto 0) 10s: in std logic vector (9 downto 0) 14 end entity AOI; 16 -start of architectire design | 17 |-architecture declaration 19 architecture v1 of AOI is 20 signal result :Integer range 0 to 31; 21 abegin 22 --end of architecture declaration and start of architecture assignment 23 ledr