Hello, I hope to help me answer this question without hanwriting, please!

a) Figure 4.1 below shows the instruction pipelining of processor. In the figure below, there is a delay in step 2 of instruction 3 (circled in red) Illustrate one reason of this delay. (0.5 mark) Pipelining step step 2 Instruction 3p step step 2 step step 4 Instruction 2 step 2 step Instruction 1 Step step 4 4 6 Time Figure 4.1: Instruction pipelining of processor b) What is the basic difference between scalar and superscalar architecture? (0.5 mark) c) There is a set of steps on accessing the memory cache. Explain these steps. (O.5 mark)