Hello, I just need help creating the primitive flow map and reduced state table for an Intel parallel IO chip

Design, simulate, implement, and demonstrate a Parallel I$/$O chip $($PIO$)$ specified below. Use one Xilinx Artix$-7$ FPGA chip $($the chip that is actually mounted on your Nexys A$7$ Board$),$ DIP$-$switches, bounce$-$free switches, Bar$-$LED modules, and various buffer chips, as needed. The states of the input signals are to be set by switches, and outputs are to be displayed using LEDs. The switches representing microprocessor data output signals should be separated from the PIO's Three$-$State $($TS$),$ bi$-$directional bus signals by a TS buffer chip. The LEDs should be driven by inverting$-$output buffers to provide a true display of the status of the signals. You must provide your own parts. Functionally, this PIO can be viewed as a segment of the Intel i$82$C$55$A chip $($refer to Intel's Web site, or any recent Intel Peripheral Components Handbook for further readings$).$ The microprocessor interface signals are as follows: CE$*,$ A$0,$ RD$*,$ WR$*,$ RESET, and INTR $(*$ stands for active$-$low$),$ as well as D$0,...,$ D$7($bi$-$directional TS data bus lines$).$ On the peripheral interface, just one $8-$bit data input port P$0,...,$ P$7$ should be implemented along with supporting hand$-$shake signals STB$*,$ and IBF. The key control signals of the PIO chip $($CE$*,$ RD$*,$ WR$*,$ and STB$*)$ should be driven by bounce$-$free switches. The register model of your PIO chip consists of three registers: Data$\_$In $($selected by CE# $=0$ & A$0=0,$ for read access only$),$ Control$\_$Reg $($CE# $=0$ & A$0=1,$ for write access only$),$ and Status$\_$Reg $($CE# $=0$ & A$0=1,$ for read access only$).$ These registers are accessed while both CE$*$ and the required control signal $($RD$*,$ or WR$*,$ respectively$)$ are asserted along with the particular value of A$0$ as specified above. The bit maps of these registers and their functions are as follows: Control$\_$Reg$\mathrm{.}0$: MODE Bit if $0$: Mode $0$ input from peripheral if $1$: Mode $1$ input from peripheral Control$\_$Reg$\mathrm{.}1$: INTE $($Interrupt Enable$)$ Bit if $1$: signal INTR is enabled if $0$: INTR is disabled Status$\_$Reg$\mathrm{.}0$: IBF $($Input Buffer Full$)$ Bit Status$\_$Reg$\mathrm{.}1$: INTE $($Interrupt Enable$)$ Bit Status$\_$Reg$\mathrm{.}2$: INTR $($Interrupt Request$)$ Bit Signal RESET resets all control and status register bits, and the INTR signal to $0$ when it is asserted. RESET is active$-$high. When the PIO is set in Mode $0,$ Bit Control$\_$Reg$\mathrm{.}1$ is irrelevant $($undefined$)$ and the Status$\_$Reg is not available $($not supported$)$