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Fall 2017 Computer Architecture Quiz 5 November 21, 2017 CENG 335 Name: Class ID: 1. (30 pt) The following code fragment is esecuted using classic five-stage pipeline MIPSs Architecture. The branches are resolved in EX stage and no branch prediction mechanism is used L1: 40(R6) I\ add R3, R1, R2 addi R3, R3, 20 R1, addi R6, R6,-4 bne R6, RO, L1 a. (1o pt) Draw the pipeline diagram assuming the architecture does NOT support forwarding, but Clock Cycle add R3, R1, R2 addi R3, R3,20 SW R3,0 (R6) addi R6, R6,-4 Second Iteration LI: w R1,40 (R6) b. (10 pt) Draw the pipeline diagram assuming the architecture fully supports forwarding. Clock Cycle add R3, R1, R2 addi R3, R3,20 sw R3,0 (R6) addi R6, R6,-4 bne R6, RO, L1 Second lteration LI: 1w R1 , 40 (R6) (10 pt) Assuming that R6 initially holds 100, how many clock cycles are needed to execute the entire loop for part a and part b? Part A: Part B: c