HELP, Please add steps for writing codes

Question 01:

1. Design by writing a VHDL code and by using state machine design a sequential circuit that has asynchronous rest and raising edge clock inputs, and 3-bit Q output. The circuit gives the following outputs: 000, 010, 100, 110, 001, 011, 101, 111, and then 000, ...etc.

2. Simulate your design and show all possible outputs and the effect of rest input. Upload the written VHDL code (No screen shot). And screen shots for simulation results, RTL schematic, and technology map viewer.

Question 02:

Solve it and Upload the written VHDL code (No screen shot). And screen shots for simulation results, RTL schematic, and technology map viewer.

Design a 4-bit shift register and counter using VHDL in one design with the following specifications: the design should have 7 inputs (sel, shift, clk, load, Clear, Prest, and D(3:0)), one output (Q(3:0)), and operate as a counter when sel=1 and as a shift register when sel=0, the Shift Register/Counter Functions are given in the following table: [19 Points