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Spring 2016 CENG 3351 Computer Architecture pt) Show the pipeline timing diagram for one iteration of the loop using the classic five-stage MIPS ure. For all parts, assume that register read and register write can be done in the same clock cyele and branches are resolved in EX stage (i e, the branch target address will be known at the end of the target instruction can be fetched in the next clock cycle). There is no branch prediction EX stage and mechanism employed loop: 1w 1, s2) addi sl, sl, 1 addi s2, 2, 4 sub s4, s3, s2 bne s4, zero, loop (6 pts) Show the pipeline timing diagram of this instruction sequence assuming forwarding is not supported by the architecture. a. addi 1, al. s2, 0(s2) sub 4. 3,2 bne s4, zero, loop b. (6 pts) Do the same work in part (a) assuming forwarding is fully supported by the architecture. 123 4 56 789 10 11 12 13 addl #1, s1, 1 2, 0(s2) addi s2, s2, sub 4, 3, 2 bne s4, zero,loop ai, 0(s2) Spring 2016 CENG 3351 Computer Architecture pt) Show the pipeline timing diagram for one iteration of the loop using the classic five-stage MIPS ure. For all parts, assume that register read and register write can be done in the same clock cyele and branches are resolved in EX stage (i e, the branch target address will be known at the end of the target instruction can be fetched in the next clock cycle). There is no branch prediction EX stage and mechanism employed loop: 1w 1, s2) addi sl, sl, 1 addi s2, 2, 4 sub s4, s3, s2 bne s4, zero, loop (6 pts) Show the pipeline timing diagram of this instruction sequence assuming forwarding is not supported by the architecture. a. addi 1, al. s2, 0(s2) sub 4. 3,2 bne s4, zero, loop b. (6 pts) Do the same work in part (a) assuming forwarding is fully supported by the architecture. 123 4 56 789 10 11 12 13 addl #1, s1, 1 2, 0(s2) addi s2, s2, sub 4, 3, 2 bne s4, zero,loop ai, 0(s2)