Help to give the full solution and answer with the VHDL code.

Figure $5$a shows the tileck diapram of a serial adder. The serial adder ialds

two gbar unsignod rumber A iad $B$ and probuces the sum in the Sum$-$

regiser. The heart of the serial wdder is in Adder Finite Stawe Mockhine

$($FSM$)$ as stown in Flgure $5$th$.$ The sale of the FSM is the caery$-$in from the

previous bit position, and it is drenotod by $G=0\%H=1.$

Figure $5$a: Bhock diaggam for the sirial adber.

Figure $5$b: Circuit for the adice FSM$.$

a$)$ Coeplete the tahle below for the stawe transition iad the cutpos sum.

$(4$ marks$)$

B$)$ Write a VHD$1.$ cose to implement the addor FSM$,$ arcoeding to the table

above Explain the bgic and algorithes try meseingful and explanatory

cometents in the code. Capture the screentiont of the source code in the

Vivabo software etwimonment.

$(5$ marks$)$

c$)$ Syuthusize and implement the design. Captume the screeminnts of the

shematic diagriet probured by Vivalo. You may combine b$)$ and c$)$ in

cele screcestost.

d$)$ Write a west bentich cose to simulate the circuit furction. In the west berich

cobe, a clock sigral shifs two $8$thit unsigned rumbers, $A=a_y{a}_s-.a_4$

and $B=b_7{B}_{5}dots{B}_0$ to the right bit by tir linto the AdSer FSM and shifts

the outper s into the sum$-$regisier. Capoure the seroershos of the trost

berch oode in the Vivalo developencent emircetment.

e$)$ With $A=00111011h$ and $B=010111006,$ run the simulation to obtain

the sum s$.$ Copture the screntishot of the simularion result. Coenpare with

the wsult with the binary wddition, and show whothof the simulation

result is carrect.