Help with question 2 please.

Assume that you have a system that contains a 16-word cache (C=16). Consider the following RISC-V assembly code addi to, zero, 4 addi so,zero,0 loop: beq to, zero, done Iw t1,ex30(s1) Iw t2,074(51) Iw t3,054(51) (w t3,050(51) addi to, to, 1 j loop done: Part2: Two-way Set Associative Cache, b = word 1) Fill in the correct size for the cache fields (Memory Address size is 32-bit): 2)Place every instruction's data in the correct set in the cache. Also, determine what kind of miss the instruction faces. 3) Find the miss rate (NOTE: if the number is 88.777778, then your answer should be 88.8 ) : (Note: number of misses includes both compulsory and the conflict misses in all iterations) Cache miss rate = % Assume that you have a system that contains a 16-word cache (C=16). Consider the following RISC-V assembly code addi to, zero, 4 addi so,zero,0 loop: beq to, zero, done Iw t1,ex30(s1) Iw t2,074(51) Iw t3,054(51) (w t3,050(51) addi to, to, 1 j loop done: Part2: Two-way Set Associative Cache, b = word 1) Fill in the correct size for the cache fields (Memory Address size is 32-bit): 2)Place every instruction's data in the correct set in the cache. Also, determine what kind of miss the instruction faces. 3) Find the miss rate (NOTE: if the number is 88.777778, then your answer should be 88.8 ) : (Note: number of misses includes both compulsory and the conflict misses in all iterations) Cache miss rate = %