helpWhen $s$ becomes $1,$ the machine changes to state $S2.$ The decision box below the state box for

$S2$ checks whether $A=0.$ If so$,$ the bit$-$counting operation is complete; hence the machine

should change to state $S3.$ If not, the FSM remains in state $S2.$ The decision box at the bottom

of the chart checks the value of $a_0.$ If $a_0=1,B$ is incremented, which is indicated in the chart

as BlarrB$+1.$ If $a_0=0,$ then $B$ is not changed. In state $S3,B$ contains the result, which is the

number of bits in A that were $1.$ An output signal, Done, is set to $1$ to indicate that the algorithm

is finished; the FSM stays in $S3$ until $s$ goes back to $0.$

$(7$ marks$)$

$($i$)$ Design the Datapath circuit of the ASM$-$Chart.

$($ii$)$ Give the ASM$-$Chart for the control circuit corresponding to part $($i$).$

c$)$ Design a schematic circuit for a Moore$-$type FSM that has an input $w$ and an output $z.$ The

machine has to generate $z=1$ when the previous two values of $w$ are $11$ ; otherwise, $z=0.$ An

example of the desired behavior is given below.

$(4$ marks$)$