Here is a sample simulation work for a 4 bit multiplier. I believe this will help for N/2 bit multiplier as required . i'm stuck in this problem..please help me out ASAP.

Course Name: Computer Organization & Architecture Design and Simulation of a N-bit MIPS CPU/M Objectives: Part #1- Design and simulation of a N-bits ALU with the following functional specification (e.g., Block diagram, Truth Table). Here N=27 ALUop 3 A ALU Zero Result N Overflow B N CarryOut Inputs Outputs ALUOp Funct field. Fx Operation Binvert Ainvert F5 F4 F3 F2 F1 FO 0 0 010 010 (add) 1 0 XO110 (sub) 1 1 X o 011 (nand) 1 1 X 1 100 (nor) 0 0 0 1 000 (and) 0 0 10 001 (or) 0 0 111 (mult) Truth table for ALU control bits 11 Design Process (with K-map QM-method etc.): Result of simulation (using LogiSIM: Discussion improvements, debriefs etc.): Simulation: legs outle of Antar Lab 06 to Aye Simulate Window Help ADDD VELG bute AD Gales Per Arco 20 - EAN Circuit: multiplier mutple Org del Sabi facing Sissed abd hunt San Serk Fan 12 CO CS co CO 02 C: Figure: Logisim Simulation Screenshot Course Name: Computer Organization & Architecture Design and Simulation of a N-bit MIPS CPU/M Objectives: Part #1- Design and simulation of a N-bits ALU with the following functional specification (e.g., Block diagram, Truth Table). Here N=27 ALUop 3 A ALU Zero Result N Overflow B N CarryOut Inputs Outputs ALUOp Funct field. Fx Operation Binvert Ainvert F5 F4 F3 F2 F1 FO 0 0 010 010 (add) 1 0 XO110 (sub) 1 1 X o 011 (nand) 1 1 X 1 100 (nor) 0 0 0 1 000 (and) 0 0 10 001 (or) 0 0 111 (mult) Truth table for ALU control bits 11 Design Process (with K-map QM-method etc.): Result of simulation (using LogiSIM: Discussion improvements, debriefs etc.): Simulation: legs outle of Antar Lab 06 to Aye Simulate Window Help ADDD VELG bute AD Gales Per Arco 20 - EAN Circuit: multiplier mutple Org del Sabi facing Sissed abd hunt San Serk Fan 12 CO CS co CO 02 C: Figure: Logisim Simulation Screenshot