Question: here is my log file and python code I am simulating mesi protocol, lecturer said there is a small bug I cannot find it can
here is my log file and python code I am simulating mesi protocol, lecturer said there is a small bug
I cannot find it can you spot any bug here
C WR at address Hit
C WR at address Hit
C WR at address Hit
C RD None at address Miss
C RD None at address Miss
C WR at address Hit
C WR at address Hit
C RD None at address Miss
C WR at address Hit
C RD None at address Miss
C WR at address Hit
C WR at address Hit
C WR at address Hit
C WR at address Hit
C RD None at address Miss
C RD None at address Miss
C RD None at address Miss
C RD None at address Miss
C RD None at address Miss
C WR at address Hit
C WR at address Hit
C RD None at address Miss
C WR at address Hit
C RD None at address Miss
C RD None at address Miss
C RD None at address Miss
C WR at address Hit
C RD None at address Miss
C WR at address Hit
C WR at address Hit
C RD None at address Miss
C RD None at address Miss
C RD None at address Miss
C WR at address Hit
C RD None at address Miss
C RD None at address Miss
C RD None at address Miss
C RD at address Hit
class MESIProtocol:
def initself cores:
self.cores cores
def readself core, address:
sharingcores c for c in self.cores if c core and self.findlineincacheccache, address
line self.findlineincachecorecache, address
if not line:
line self.loadlinefrommemorycore address, sharingcores
if line.state I:
if anyccache.findlineincacheaddressstate M for c in sharingcores:
for c in sharingcores:
self.flushifmodifiedccache.findlineincacheaddress
ccache.findlineincacheaddressstate S
line.state S if sharingcores else E
return line.value
def writeself core, address, value:
self.invalidateotherscore address
line self.findlineincachecorecache, address
if not line:
line self.loadlinefrommemorycore address
if line.state E or line.state S:
self.flushifmodifiedline
line.value value
line.state M
def invalidateothersself core, address:
for othercore in self.cores:
if othercore core:
line self.findlineincacheothercore.cache, address
if line and line.state I:
self.flushifmodifiedline
line.state I
def loadlinefrommemoryself core, address, sharingcores:
isshared anyselffindlineincacheccache, address for c in sharingcores if c core
line core.cache.replacelinecorecache.findlineaddress address, core.memory.storageaddress False
line.state S if isshared else E
return line
def findlineincacheself cache, address:
setindex cache.findlineaddress
set cache.setssetindex
for line in set:
if line.address address and line.valid:
return line
return None
def flushifmodifiedself line:
if line.state M:
line.memory.storagelineaddress line.value # Flush to memory
line.dirty False
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