Hi, I need codes and state diagram for this problem please, and can you also explain this question and answer as much you can. I will be very thankful to you.

DESCRIPTION Sequence detectors are very important in a variety of applications. The main objective of this group project is to implement a sequence detector for FPGAs. A simulation of the NEXYS FPGA board will be used for the prototyping and testing of the implemented system (see board schematic on the next page). You are asked to take the steps below for your implementation and presentation: 1. Using Vivado, write VHDL code for the implementation of a sequence detector in VHDL using push buttons. Four push buttons should be used for entering symbols ('1','2','3','4') and one push button should be used for initialisation. Up to 12 symbols could be entered after pressing the initialisation push button. When the sequence "1 4 2 3 3" is entered, then the LEDs should start flashing. Please note that the right sequence of symbols need not necessarily be entered immediately after the initialisation push button is pressed. For example, the sequence 1 2 3 4231123314233 should be able to activate the flashing of the LEDs. If 12 symbols have been entered but the right sequence of symbols has not appeared yet, then the system should lock and the LEDs should show the following predefined pattern: on, off, on, off, on, off, on, off, on, off, on, off. If the system is locked, the user will need to press the initialisation button in order to be allowed to start entering new symbols. 2. Synthesise and implement your design (in your report present the RTL and technology schematics). 3. Analyse the code (produce summary) and give a brief description of your implementation. 4. Use simulation to test your design and display input/output results with a brief description. 5. Generate bit-stream. estimate in your