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Digital system design

4). A circuit is needed to start and stop counting clock pulses on command. (a) Design a 3-bit synchronous counter that goes through the sequence 000,001,010, 011,100,101,110,111 and then repeats. Use positive-edge-triggered JK flip-flops. Label the bits Qc,QB \& Q where Qc is the most significant bit. Draw the circuit implementing the counter. [15pts] (b) Modify the circuit so that it counts whenever an additional COUNT ENABLE (CTE) input is HIGH, stops counting when CTE goes LOW and resumes counting from where it stopped when CTE goes HIGH again. [5 pts]