Homework $\backslash$#$9$

$1.$ Convert by adding external gates:

a$.$ A JK flip$-$flop into a D flip$-$flop

b$.$ A JK flip$-$flop into a T flip$-$flop

c$.$ An T flip flop into an SR flip flop.

$2.$ Consider the circuit given on the right. For this circuit, assume the $\backslash ($ D $\backslash )$ and clock signals are applied as shown below. Draw the waveforms for the signals $\backslash ($ Q a$,$ Q b $\backslash )$ and $\backslash ($ Q c $\backslash ).($Note: Identify the circuit diagrams for latch, flip$-$flop, and flip$-$flop with falling

edge sensitive clock before drawing the waveforms$).$

$3.$ Complete the table for the circuit below:

$4.$ Implement a JK flip flop using Verilog.

$5.$ Implement a $6-$bit, modulo$-50,$ up counter using Verilog. You only need to have an enable $($E$)$ and a clock $($Clk$)$ as inputs.