How many clocks does it take for a change in Datain to be reflected on DataOut?

module BitReverser

$($

input logic Clk$,$

input logic Rst$,$

input logic $[7$:$0]$ DataIn,

output logic $[7$:$0]$ DataOut

$)$;

$(11)$

$12$

assign DataOut $[7]=$ DataIn$[0]$;

assign DataOut$[6]$ DataIn$[1]$;

assign DataOut$[5]=$ DataIn$[2]$; assign DataOut$[4]=$ DataIn$[3]$;

assign DataOut$[3]=$ DataIn$[4]$;

assign DataOut$[2]$ DataIn$[5]$;

assign DataOut$[1]$ DataIn$[6]$;

assign DataOut $[0]$ DataIn $[7]$;

Logic Complexity

$(13)$

endmodule

$9$

$15$

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$00$

$01$

$04$

$08$

Code Examgile $1-$

$18$

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