How many general purpose $($integer$)$ registers has the $x86$ architecture in $32$ bit mode?

Draw the timing diagram for a CPU with a classic five stages RISC pipeline. The stages are instruction fetch $($IF$),$ instruction decode $($ID$)$ and execute $($EX$),$ memory access $($MEM$)$ and write back $($WB$).$

What is a write$-$after$-$read hazard?

Describe the five stages of the $80486$ pipeline.

The Intel $8088$ CPU contains a bus interface unit $($BIU$)$ and the execution unit $($EU$).$ Together these two form a two stage pipeline. Suppose that the EU stage requires twice as much time for each instruction than the BIU. By what factor does the pipeline improve the CPU's performance?

What are the typical characteristics of a RISC system?