How would I go about this in the Python language?

1 Simulating a Hardware Memory Cache You'll write a program to simulate the behavior of a hardware memory cache. You can use the language of your choice. You may work either by yourself or with a partner. If you're working with a partner, the due date is Monday, Mar. 1st at 11:59 pm; if you're working alone, the due date is Saturday, Mar. 6th at 11:59 pm. 1.1 Memory hierarchy Model memory as an array of bytes. Each memory access will read or write one word (four bytes). Check that each address is aligned on a four-byte boundary, and assert if it isn't. Also check that each memory access is in range, and assert if it isn't. So for example if memory [56] 45 and memory [57] = 12 and memory [58] = 3 and memory [59] = 7, then the word referenced by address 56 would be 45 + 256 * (12 + 256 * (3 + 256 * 7)) 117640237 (assume a little-endian system). When a range of values is loaded into the cache, the number of bytes loaded will thus be a multiple of four. 1.3 Parameters Your simulator should let you specify these parameters: the size of a memory address, in bits the size of the cache, in bytes this size of a cache block, in bytes the associativity of the cache whether the cache is a write-back or write-through cache Do not hardcode any of these values they should be configurable. Use a variable or a #define to represent each of them. But, assume a write-allocate cache: on a write miss, the block containing the memory address in question is first brought into the cache. 1.5 Functions Create two functions: one to read a word from memory, and one to write a word to memory. For example: in C, my functions would look like this: Word readWord (unsigned int address); void writeWord (unsigned int address, Word word); Word is a typedef to an int. In Python, I might do this: readWord (address) writeWord(address, word) where readWord returns the value read from the specified address. Again, check each address for four-bit alignment and for range 0