how would this look like as a VHDL code for example sothing like this.

Segment a: A+C+BD+BD Segment b: B+CD+CD Segment c: B+C+D Segment d: A+CD+BC+BD+BCD Segment e: BD+CD Segment f: A+CD+BC+BD Segment g: A+CD+BC+BC LIBRARY ICEe; USE Ieee.std'logic 1164. ALL; EENTITY SevenD IS PORT A,B,C, D: IN std_logic: a,b,c,d,e,f,9: OUT std_logic); END SevenD; ARCHITECTURE arC OF SEVenD IS BEGIN ac=AOR[C OR (B AND D) OR not (b OR d)