Figure 4.5 depicts the voltage-divider bias circuit for an n-channel enhancement- mode MOSFET, a popular circuit...

  

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Figure 4.5 depicts the voltage-divider bias circuit for an n-channel enhancement- mode MOSFET, a popular circuit to create a stable operating point in spite of changing environmental temperature and device-to-device variations. In this problem the load line graphical analysis technique establishes the drain current operating point. www RG1 RG2 VDD RD ID VGS ww RS VD Figure 4.5: Circuit for Problem 4.5 Analysis 1. Use a suitable plotting tool such as Mathscript or MATLAB to plot the transistor drain current Ip as a function of gate-source voltage VGs when the device operates in saturation mode; use the transistor parameters listed in the table below. Set up the plot limits as 0 to 3 volts for VGs and 0 to 50 mA for Ip. 2. Draw the load line established by the voltage divider resistors RG1 and RG2, the supply voltage VDD, and the source resistor Rs directly on the transistor curve from the previous step. Identify the circuit's Figure 4.5 depicts the voltage-divider bias circuit for an n-channel enhancement- mode MOSFET, a popular circuit to create a stable operating point in spite of changing environmental temperature and device-to-device variations. In this problem the load line graphical analysis technique establishes the drain current operating point. www RG1 RG2 VDD RD ID VGS ww RS VD Figure 4.5: Circuit for Problem 4.5 Analysis 1. Use a suitable plotting tool such as Mathscript or MATLAB to plot the transistor drain current Ip as a function of gate-source voltage VGs when the device operates in saturation mode; use the transistor parameters listed in the table below. Set up the plot limits as 0 to 3 volts for VGs and 0 to 50 mA for Ip. 2. Draw the load line established by the voltage divider resistors RG1 and RG2, the supply voltage VDD, and the source resistor Rs directly on the transistor curve from the previous step. Identify the circuit's