Question: I have a question about direct addressing caches Given a direct mapped cache with 4k lines and 16 bytes in a line in a 32

I have a question about direct addressing caches

Given a direct mapped cache with 4k lines and 16 bytes in a line in a 32 bit addressing environment:

How many address bits are required for byte select?

How many bits are required for cache index (line select)?

How many bits are there in each tag entry?

How many pages does this cache split the main memory into?

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Also, given a 4 way set associative cache with 1k sets and 16 byte in a line:

How many address bits are required for byte select?

How many bits are required for cache index (line select)?

How many bits are there in each tag entry?

How many pages does this cache split the main memory into?

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