I have a vhdl code where in the attached image I have a bit mapped designed digit that i want to display. I have everything working but I want to make the bit maps be read in from a file. I have the digits $0-9,$ a colon $"$:$",$ and a blank space. can someone show me how to read the bit maps from a different file directly into the varaibles i have as now. An example is "constant BM$\_9\_$dig:DigitDesign:$=",$ and this is the varaible for the digit design.

type DigitDesign is array $(0$ to $79)$ of std$\_$logic$\_$vector$(0$ to $39)$;

and finally i need each possible of the digits to be set equal to BM$\_""\_$dig, where the $""$ is supposed to be $0-11,$ where the bit maps for $0,1,2,3,$etc. are suposed to be equal to BM$\_0\_$dig, BM$\_1\_$dig, ect. and the blank spot is BM$\_10\_$dig, and the colon is BM$\_11\_$dig