I have completed #1a, help is needed for #1b

The circuit below is to apply XOR operations over all bits of an input signal. Note that this circuit returns 1 if there is an odd number of ones in its input. (This circuit can be used to determine the odd parity of the input signal).

a.Write VHDL code to describe an 8-bit XOR tree over a(0) a(7) as y = a(0) xor a(1)xor a(2)xor a(3) xor a(4) a(5) xor a(6) xor a(7)

Library ieee;

Use ieee.std_logic_1164.all;

Entity xor is

Port( a : in std_logic_vector(7 downto 0);

Y : out std_logic

);

end xor;

architecture behavioral of xor is

begin

Y <= ((a(0) xor a(1)) xor (a(2) xor a(3))) xor ((a(4) xor a(5)) xor (a(6) xor a(7)));

End behavioral;

*HELP IS REQUIRED HERE* >>>> b.Modify your code for an XOR tree with arbitrary input size of m-bit based on the figure below.