Question: I have provided question and solution both.Please explain clearly. Refer: Computer Architecture: A Quantitative Approach, 6th Edition, Hennessy and Patterson, Morgan Kaufmann Publishers, Inc., 2019,

 I have provided question and solution both.Please explain clearly. Refer: Computer

Architecture: A Quantitative Approach, 6th Edition, Hennessy and Patterson, Morgan Kaufmann Publishers,

Inc., 2019, ISBN: 978-0-12-811905-1. [20 pts] 5- Consider the implementation of the

I have provided question and solution both.Please explain clearly.

Refer: Computer Architecture: A Quantitative Approach, 6th Edition, Hennessy and Patterson, Morgan Kaufmann Publishers, Inc., 2019, ISBN: 978-0-12-811905-1.

[20 pts] 5- Consider the implementation of the Tomasulo's algorithm with Reorder Buffer (ROB) shown below. It consists of four stages: Issue, Execute, Write-back, and Commit. Simulate the execution of the following piece of code using Tomasulo's algorithm and show the contents of the RS, ROB, and register file entries for each cycle (shown in the following page). - An ROB entry contains three fields: - Committed - Yes (committed) and No (not committed) - Dest-destination register identifier - Data - value - In addition to the Busy and Value fields, a register contains ROB \# that indicates the ROB entry that will generate the result. - In addition to Op, Busy, Vj,Vk,Qj, and Qk fields, a RS contains Dest field that indicates the ROB entry where the result will be written to. (I left out Busy field because of lack of space). Assume the following: (1) Dual issue, write-back, and commit, i.e., two instructions can be issued, forwarded to the CDB, and committed per cycle; (2) add/subtract latency is 1 cycle and multiply/divide latency is 3 cycles; (3) an instruction can begin execution in the same cycle that it is issued, assuming all dependencies are satisfied. Also, forwarded results are immediately available for use in the next cycle. Note that this code takes exactly 8 cycles to complete! MUL.D F0,F2,F4 SUB.D F8,F2,F6 DIV.D FO,F0,F6 ADD. D F6,F8,F2 \begin{tabular}{l|c|c|c|c|c|c|} \multicolumn{1}{c}{ Op } & \multicolumn{1}{c}{Dst} & Vi & Qi & Vk & Qk \\ \cline { 2 - 7 } & ADD.D & 3 & & 1 & 3.5 & \\ \hline & & 4.3 & & & \\ \cline { 2 - 7 } 3 & & & & & \\ \cline { 2 - 7 } & & & & & & \\ \hline \multicolumn{6}{c|}{ Add/Sub } \end{tabular} Value=0.8,Best=3(ROB#) \begin{tabular}{c|c|c|c|c|c|c|} \multicolumn{1}{c}{ Op } & Dst & Vj & Qj & Vk & Qk \\ \cline { 2 - 7 } \\ \cline { 2 - 7 } \\ \cline { 2 - 7 } & & & & & & \\ \cline { 2 - 7 } & & & & & \\ \cline { 2 - 7 } & & & & \\ \hline \multicolumn{6}{c|}{ Add/Sub } \end{tabular} Value=35.0,Dest=0(ROB#) \begin{tabular}{c|c|c|c|c|c|c|} \multicolumn{1}{c}{ Op } & \multicolumn{1}{c}{ Dst Vj} & Qj & Vk & Qk \\ \cline { 2 - 7 } \\ 2 & & & & & & \\ \cline { 2 - 7 } & & & & & & \\ \cline { 2 - 7 } & & & & & \\ \hline \multicolumn{6}{c|c}{ Add/Sub } \end{tabular} Dest =0 does not match. ROB\# Value=4.49 Dst =2 (ROB\#) Nisis ru Keglster Fue 4 1 1 1 1

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