Question: I ' m trying to complete this prompt: Create a Reaction Time Monitor ( RTM ) that can indicate how quickly an user can respond

I'm trying to complete this prompt: "Create a Reaction Time Monitor (RTM) that can indicate how quickly an user can respond to a stimulus. In operation, the RTM is initialized when a start button is pressed. Immediately after the start button is pressed, the 7seg display is set to show all 0s, and then a random time later (between about 1 and 10 seconds), a react now LED illuminates and a millisecond timer starts. When the timer starts, the 7seg display shows the timer value as it counts up in milliseconds.
As quickly as possible after the react LED illuminates, the user must press a react button to stop the timer. The stopped timer will contain the number of milliseconds between the react LED being illuminated and the button being pressed, and that time will be shown on the 7seg display. Pressing the start button again will clear the timer and begin a new round."
For some reason the react led only has a delay every other time I press the start button and I cant figure out why ```
module ReactionTimeMonitor (
input clk,// System clock
input reset, // Reset signal
input start_button, // Start button
input react_button, // React button
output reg [6:0] seg, //7-segment display
output reg [3:0] an,// Display digit selector
output reg react_led // React LED output
);
// Parameters
localparam IDLE =2'b00;
localparam WAIT_DELAY =2'b01;
localparam LED_ON =2'b10;
localparam DISPLAY =2'b11;
localparam CLK_FREQ =100_000_000; //100 MHz
localparam DELAY_MIN =1; // Minimum delay in seconds
localparam DELAY_MAX =10; // Maximum delay in seconds
// Internal registers
reg [1:0] state, nstate; // FSM state and next state
reg [31:0] delay_counter; // Delay counter
reg random_calculated; // Random delay flag
reg [15:0] random_seed; // LFSR for random delay
```
```
reg [16:0] clk_divider; // Clock divider for 1kHz
reg clk_1khz; _//1kHz clock
reg [1:\overline{0}] mux_sel; // Display digit selector
reg [3:0] bcd_mux; // Current BCD digit for
display
reg [31:0] timer;
// Debounced buttons
wire start_debounced, react_debounced;
debounce debounce_start (
.clk(clk),
.reset(reset),
.switch_in(start_button),
.debounced(start_debounced)
);
debounce debounce_react (
.clk(clk),
.reset(reset),
.switch_in(react_button),
.debounced(react_debounced)
);
// Generate 1kHz clock
always @(posedge clk or posedge reset) begin
if (reset) begin
clk_divider =0;
clk_1khz =0;
``````
end else if (clk_divider ==17'd49999) begin
clk_divider =0;
clk_1khz = ~clk_1khz;
end else begin
clk_divider = clk_divider +1;
end
end
// Pseudo-random number generator (LFSR)
// Random delay setup (1 to 10 seconds)
always @(posedge clk or posedge reset) begin
if (reset) begin
delay_counter =32'd0;
random_calculated =1'b0;
end else if (state == WAIT_DELAY && !random_calculated) begin
delay_counter =((random_seed[6:0]%(DELAY_MAX - DELAY_MIN +
1))+ DELAY_MIN)* CLK_FREQ;
random_calculated =1'b1; // Set once random delay is calculated
end else i\overline{f}(state == WAIT_DELAY && delay_counter >0) begin
delay_counter = delay_counter -1;
end else if (state == IDLE) begin
random_calculated =1'b0; // Reset flag in IDLE
end
end
// Pseudo-random number generator (LFSR)
always @(posedge clk or posedge reset) begin
if (reset) begin
random_seed =16'hACE1; // Arbitrary non-zero seed
end else if (state == IDLE) begin
random_seed = random_seed ^ timer[15:0]; // Add variability with
timer
end else begin
random_seed ={random_seed[14:0], random_seed[15]^
random_seed[13])};
end
end
// FSM Logic
always @(posedge clk or posedge reset) begin
if (reset) begin
state = IDLE;
end else begin
state = nstate;
end
end
always @(*) begin
case (state)
IDLE: begin
if (start_debounced) begin
nstat\overline{e = WAIT_DELAY;}\\
end else begin
``````
nstate = IDLE;
end
end
WAIT_DELAY: begin
if (delay_counter ==0) begin
nstate = LED_ON;
end else begin
nstate = WAIT_DELAY;
end
end
LED_ON: begin
if (react_debounced) begin
nstate = DISPLAY;
end else begin
nstate = LED_ON;
end
end
DISPLAY: begin
if (start_debounced) begin
nstate = IDLE;
end else begin
nstate = DISPLAY;
end
end
default: nstate = IDLE;
endcase
end
// Timer Logic
always @(posedge clk_1khz or posedge reset) begin
if (reset) begin
bcd0=4'b0000;
bcd1=4'b0000;
bcd2=4'b0000;
bcd3=4'b0000;
end else if (state == LED_ON) begin
if (bcd0==4'b1001) begin
bcd0=4'b0000;
if (bcd1==4'b1001) begin
bcd1=4'b0000;
if (bcd2==4'b1001) begin
bcd2=4'b0000;
if (bcd3==4'b1001) begin
bcd3=4'b0000; // Overflow, reset
end else begin
bcd3= bcd3+1;
end
end else begin
bcd2= bcd2+1;
end
end else begin
bcd1= bcd1+1;
```
bcd0= bcd0+1;
end
end
end
// React LED logic
always @(posedge clk or posedge reset) begin
if (reset) begin
react_led =1'b0;
end else if (state == LED_ON && !react_debounced) begin
react_led =1'b1;
end else begin
react_led =1'b0;
end
end
// Display MuX
always @(posedge clk_1khz or posedge reset) begin
if (reset) begin
mux_sel =2'b00;
end else begin
mux_sel = mux_sel +1;
end
end
always @(*) begin
case (mux_sel)
2```
4'b0110:
I ' m trying to complete this prompt:

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