Question: I m writing a code in verilog for interfacing fpga spartan 3 with Keypad 4x4 membrane -I m able to write the code the problem
I m writing a code in verilog for interfacing fpga spartan 3 with Keypad 4x4 membrane
-I m able to write the code the problem woth the code is i m unable to latch the value of key once i pressed the coloum input of any keypressd it take the value and change the value key and doesnot store the value of key untill or unless another coloum is pressed so it chnage value and goes back go default value that i have attached in code
-I want to latch the value of key untill or less another key is pressed amd chnage it's output value
-Codee:
module keypad_code(
input clk,
input rst,
input pulse,
input [3:0] col,
output reg [3:0] row,
output reg [3:0] key
);
reg [3:0] counter_cs;
reg [3:0] counter_next;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
counter_cs <= 4'b0000;
end
else
begin
counter_cs <= counter_next;
end
end
always@(*)
begin
if(pulse)
begin
if(counter_cs > 4'b1001)
begin
counter_next = 4'b0000;
row = 4'b0000;
end
else
begin
counter_next = counter_cs + 4'b0001;
row = counter_cs;
end
end
else
begin
counter_next = counter_cs;
row = counter_cs;
end
end
always@(*)
begin
case(row)
4'b0001:
begin
case(col)
4'b0001: key = 4'b0000;
4'b0010: key = 4'b0001;
4'b0100: key = 4'b0010;
4'b1000: key = 4'b0011;
default: key= 0;
endcase
end
4'b0010:
begin
case(col)
4'b0001: key = 4'b0100;
4'b0010: key = 4'b0101;
4'b0100: key = 4'b0110;
4'b1000: key = 4'b0111;
default: key = 0;
endcase
end
4'b0100:
begin
case(col)
4'b0001: key = 4'b1000;
4'b0010: key = 4'b1001;
4'b0100: key = 4'b1010;
4'b1000: key = 4'b1011;
default: key= 0;
endcase
end
4'b1000:
begin
case(col)
4'b0001: key = 4'b1100;
4'b0010: key = 4'b1101;
4'b0100: key = 4'b1110;
4'b1000: key = 4'b1111;
default: key = 0;
endcase
end
default:
begin
key = 0;
end
endcase
end
-i m open to anything you can make another module or anything to latch the output value of key
-all inputs coloum goes through a debouncer already so no problem with that
-pulse signal is just clock divder signal which high for 1Hz
-i m open to suggestions
PS: i m using Xilinix ISE as a platform
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