I need a register file VDHL code with two read ports ( A1, A2) and one write port (A3). The width of A1, A2 and A3 is 5 bits.

Writing data into the register is synchronized with the clock signal. WE is the write enable

control signal. WD contains the data for the write operation.

And please give me a screenshot of the simulation.

CLK WE3 A1 RD2 ?? WD3 Register 32 CLK WE3 A1 RD2 ?? WD3 Register 32