I need a Verilog code with a test bench for the FSM and the ALU plus the top modules as well. For the second milestone, you are required to check o

project$-$specific items with your lab TA by

its deadline. You are required to complete the tasks below. Make sure you also refer to each project

for its specific required items.

$$ Revised high$-$level FSM or ASM chart, datapath design, and controller FSM$.$

$$ Verilog implementation of all modules of your design with verified syntax check from Vivado.

Refer to each project for its specific required modules.

$$ Testbench for all modules and verification in the Vivado simulator.

$$ Be prepared to explain your Verilog description and simulation results in a clear and logical

manner, and answer questions about your design from your lab TA at check$-$o

$.$

$$ Once you complete the above items, demonstrate your implementation on the Basys$3$ board

to your lab TA$.$

$$ Pay attention to projects $4$ and $5$ for the requirements on board implementation.

Project$-$Specific Check$-$o

Requirements

$1$ Simple ALU calculator

$$ Controller FSM module.

$$ Datapath modules: Verilog description of all datapath components in your revised high$-$level

design from the first milestone.

$$ Top$-$level module: Top$-$level Verilog module describing connections between datapath compo$-$

nents and controller.