I need help with Question 2 and question 4 a and b both.

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4. Consider the following sequence of instructions executed on the basic 5 stage pipeline. add $t3, $t2, $t1 sw $t5, 0 (Ss3) and $t6, $t7, $t4 add $t7, $t5, $tl a) Assuming our processor has no forwarding or hazard detection, insert a minimal amount of pipeline stalls to ensure correct execution (you may stall the pipeline with the instruction add $zero, $zero, $zero) b) Assuming our processor has no forwarding or hazard detection, rearrange the instructions and add stalls only if necessary to ensure proper execution. The values contained in the registers after executing your modified code should be equivalent to the unmodified execution. ALU Shitt Branch Instruction 131-26 25-21 Read PCRead register 1 Read 20-16] | Read data 1 Zero regster 2 UAddress dataM (31-0 Instruction Write data 2 15-11 xregster data Registers Write Data 15-01 16 sign 32 ALU I. Consider the single stage CPU represented in the diagram. Complete the control line table below for the given instructions by entering 0,, or x for "don't care" Instruction #1: Instruction #2: Instruction #3 Instruction #4: Instruction 5 sltu $to,$t1,$t2 10101100011000100000000000010100 sh $t0,$tl,100 beq $to,St1,Li 0x026F6020 RegDst Branch MemRead MemtoReg MemWrite ALUSIC RegWrite #1 2 #4 #5 2. For each instruction in part 1, what would be the the values of the ALUop and ALU control input