I need verilog simulation in which it is required please give the solutions

HW \#02 - Due date Thursday, March 2, 2023 - All the HW should be submitted electronically along with simulation files on Canvas 6.6 Use the paper-and-pencil method to multiply the operands shown which are in 2 s complement representation. Multiplicand =11111 Multiplier =01011 6.13 Use the Booth algorithm to multiply the operands shown, which are signed operands in 2 s complement representation. Multiplicand =11001 Multiplier =10101 6.18 Use bit-pair recoding to multiply the following operands which are in 2s complement representation. Multiplicand =0100110 Multiplier =1001101 7.3 Use the sequential shift-add/subtract restoring paper-and-pencil method to divide the operands shown. The sign bit of the partial remainder determines whether to restore the previous partial remainder. Dividend A=00101111 Divisor B=0011 7.11 Use the paper-and-pencil method to perform SRT division on the following operands: dividend A.Q=0.00000111 and divisor B=0.1000. Obtain the result as a 4-bit quotient and a 4-bit remainder. 7.14 Use the paper-and-pencil method to perform SRT division on the following operands: dividend AQ=0.100111 and divisor B=0.101. Obtain the result as a 3-bit quotient and a 3-bit remainder