If a cache can deliver $0\mathrm{.}625$ of load$/$store requests from CPU, and suppose a processor has $2$ levels of hierarchy with $T_{\text{c}\text{a}\text{c}\text{h}\text{e}}=1$ cycle, and $T_{\text{R}\text{A}\text{M}}=100$ cycles. What is the AMAT?

Select one:

a$.38\mathrm{.}5$ cycles

b$.$ none

c$.24\mathrm{.}5$ cycles

Direct Mapping Cache Organization

d$.48\mathrm{.}5$ cycle

e$.63\mathrm{.}5$ cycles