II$.$ An OS is using two$-$level paging to implement a $32-$bit virtual address space per process. The page size is $1024-$bytes, and the machine does not have a TLB$.$

$($a$)$ What is the size of the inner $($or lower level$)$ page table in bytes assuming each PTE is $4$ bytes in size?

$($b$)$ What is the size of the outer page table $($the higher level$)?$

$($c$)$ Explain the steps involved in looking up the virtual address $0$x$003$bf$04$d$,$ when all pages are present in memory; explain, which bits are used to access each level of the page table. $(2$ points$)$

$($d$)($d$)$ For the system above, what is the maximum number of page faults that could be generated in response to a memory access? Explain $(2$ points$)$