$($ii$)$ For the existing project, create a new VHDL file for ALU with $\text{'}$ X $\text{'},\text{'}{Y}^{\text{'}},$ add$\_$sub, ALUOP as inputs and $\text{'}$S$\text{'}$ and 'ZERO$2\text{'}$ as output. Note that this ALU is slightly different from the MIPS ALU but the main concepts are the same. It is optimized to support the $5$ ALU operations, whereas the MIPS ALU and ALU control are designed for $16$ operations. This ALU will be used as a component and will replace the ripple carry adder in the processor. The inputs and outputs of the ALU component are shown in the Figure below. The internal structure of the ALU is shown in the second Figure below.

Figure $1$: ALU port declarations to be used