III. (10 points) Design a 16K8 (16 kilobyte) memory subsystem with high-order interleaving, using 2K8 SRAM chips, for a computer system with an 8-bit data bus and a 16-bit address bus. Show the logic to generate the necessary CE signals, which should be active high, if this subsystem corresponds to the memory address range $4000 to $7FFF. In addition, the CE signals should be active only if the activelow MREQ control signal from the CPU-which indicates that the address on the bus is a memory address-is also active. All interconnections and signal names should be clearly labeled. (Hint: Note that a 2K8 memory chip has a capacity of 2048 bytes, so you will need to use an array of eight of these chips to create a single 16K8 memory unit. Instead of using basic logic gates to generate separate CE signals for all eight chips, I suggest that you use a 3:8 decoder in your design, as we have discussed in class.)