Question: III. ( 2 0 points ) Logic gate design at transistor level: Find the Pull - down network ( PDN ) that corresponds to the

III. (20 points) Logic gate design at transistor level:
Find the Pull-down network (PDN) that corresponds to the Pull-up network (PUN) shown in Fig.6.
Draw the complete CMOS logic circuit using the PUN and PDN.
Find the logic function for the circuit you derived in 2).
III. ( 2 0 points ) Logic gate design at

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