implement a decoder eith both verilog and VHDL, and simulate them respectively and print out waveforms. In the following, testbech is provided in VHDL

library IEEE; use IEEE,std_logic 1164.311; use IeEE.std_logic_arith.all; entity DECODER TE is . entity declaration end DECOOER_TB; architecture TB of DECODER_TB is begin \[ \begin{array}{l} \text { U_DECODER: DECODER port map (T_I, T_O); } \\ \text { process } \end{array} \] - variable should be declared within process variable err_cnt : integer : =0; begin - case " 00" wait for 10 ns; TI