Implement a for-loop in software and in hardware. One implementation is a software implementation in which a Nios II assembly program is developed to perform the finding Max loop, and the other realization is a hardware (RTL) realization on an FPGA

Problem 1: Write a Nios II program to perform the following loop. Assume a memory location for n, and a memory location where dataIn begins.

max = 0 ;

for (i=1; i<=n; i=i+1) begin

if (dataIn > max)

max = dataIn;

end

Problem 2: Implement the following loop as an RT level circuit. This is a very simple accelerator that takes a software task and implements it in hardware for faster execution.

max = 0 ;

for (i=1; i<=n; i=i+1) begin

if (dataIn > max)

max = dataIn;

end

Data inputs into the circuit via its 8-bit dataIn bus, the output (max) becomes available on the circuits output bus. The circuit has a start input to start the finding max process, and a ready output that becomes 1 and stays 1 when the circuit has completed its task and is waiting for the next loop operation. A complete positive pulse on start is required to begin the operation. After start becomes 0 the dataIn input will contain the iteration number, n, on next clock edge. The next n clock pulses after that will have the maximum data. The following clock after that will set ready to 1.

A) In a diagram, show the datapath of this circuit.

B) Show a list of all control signals and their function.

C) Show a state diagram describing the controller of this circuit.

D) Write Verilog descriptions for the circuits datapath and control unit.

E) Generate a testebench for testing you circuit for several complete runs of data.

F) Make a Quartus design of this circuit and perform synthesis of the design.

G) Program a DE board to implement this circuit. Use the switches for data entry and push buttons for clocking and resetting your circuit. Use LEDs to display the output of the circuit.