Implement the following circuit using the modules that you have implemented in PART $1.$ For FFs$,$ you should use one single synchronous reset. You have $5$ input ports, i$.$e$.$ X$,$ Y$,$ Z$,$ S$0,$ S$1$ and one output port T$.$ For this part only: The TA will check your schematic and code instead of the testbench simulation. To access the schematic in Vivado, first click on $$Open Elaborated Design$.$ You should double check that your schematic matches the circuit below.

Add a synchronous reset as an input to DFF$.$

Make a new module and reuse your old code to add an asynchronous reset

to DFF$.$

Implement a positive edge triggered TFF using the DFF without the reset.

Add a synchronous reset as an input to TFF $($you can use the DFF from step

$2).$

Make a new module and reuse your old code to add an asynchronous reset

to TFF $($you can use the DFF from step $3).$

Use the DFF and now construct a JKFF$.$

a$.$ Use the DFF without reset to build a JKFF without reset.

b$.$ Use the DFF with synchronous reset to build a JKFF with

synchronous reset.

c$.$ Use the DFF with asynchronous reset to build a JKFF with

asynchronous reset.

Instantiate two versions of JKFFs with synchronous and asynchronous

resets in your top module.

a$.$ Two JKFF modules will share the same inputs J$,$ K$,$ reset, and clock.

b$.$ The final outputs of top module will be the output Q$\_$sync from JKFF

with synchronous reset and Q$\_$async from JKFF with asynchronous

reset.

c$.$ Q$\_$sync and Q$\_$async should be the outputs.

d$.$ Your testbench must test at least one case where Q$\_$sync and

Q$\_$async are different.

For each of the steps, build a test bench that shows your modules work. There are

few inputs, so test them exhaustively.

Part $1($B$)$:

Use the DFF and the clock divider provided to you and divide the system clock by $10$

to create a $10$x slower clock and use it as the clock of the DFF$.$ Run a testbench and

verify the DFF changes output at pos$-$edge of the slower clock.

CLOCK DIVIDER

The reason you want that clock to be slow is that when you move the switches $($in

case you implement the design on FPGA$),$ you can observe the DFF output. We

provided you a clock divider Verilog file $($ cl k$\_$divider.v$).$ You need to

understand the implementation of this file and make changes to satisfy required

clock frequency.

PART $1$

Part $1($A$)$:

In this part, you will implement three different types of FFs with two different reset

types. You must show your results using simulation. You must use behavioral

Verilog for the FFs$.$

Steps:

Build a positive edge triggered DFF$.($We did this step for you as an example.

Please use the given dff$.$v and dff$\_$t$.$b$.$v files$)$

Figure $1.$ The simulation output for a positive edge triggered DFF showing that the

value of Q is set to the value D at each positive edge. Please make a similar

simulation for every flip$-$flop you design and show them to the TA during the demo

at the end. for dff $`$timescale $1$ns $/1$ps

$//////////////////////////////////////////////////////////////////////////////////$

$//$ Company:

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$//$

$//$ Create Date: $02/28/202409$:$51$:$32$ AM

$//$ Design Name:

$//$ Module Name: dff

$//$ Project Name:

$//$ Target Devices:

$//$ Tool Versions:

$//$ Description:

$//$

$//$ Dependencies:

$//$

$//$ Revision:

$//$ Revision $0\mathrm{.}01-$ File Created

$//$ Additional Comments:

$//$

$//////////////////////////////////////////////////////////////////////////////////$

module dff$($

input D$,$

input clk$,$

output reg Q$,$

output notQ

$)$;

initial Q $=0$;

assign notQ $=$ ~Q;

always @$($posedge clk$)$ begin

Q D;

end

endmodule