Question: Implement the following logic function using complementary CMOS. a ) = - ( + ) ( + / + ) + 1

Implement the following logic function using complementary CMOS.
a)=-(+")(+/+")+"1
b) Size the devices such that the output resistance is the same as
that of an inverter with NMOS W n/L=2 and PMOS W p/L=6
c) Which input patterns would give the worst and the best
equivalent pull-up or pull-down resistance?

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