Implement the functions $F(a,b,c)=ab+c,$ and $G(a,b,c)=a(b+c)$ using

a$)$ One decoder of appropriate size and two OR gates

b$)$ One decoder of appropriate size and the minimal number of two$-$input OR gates

c$)$ One decoder of appropriate size and minimal number of NAND gates

d$)$ Implement $F(a,b,c)$ using one $4-$to$-1$ size multiplexer. Show your circuit